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Python Automation Engineer
1 week ago
Experience required: 4 to 5 years
Location: Pan India (Any LTIMindtree Location)
- Must have minimum 4-5 years of ASIC/FPGA development experience either in design or verification.
- Must know Verilog, SystemVerilog. Knowledge in UVM is plus.
- Must be proficient in Python and make. Experience with Jenkins is a plus.
- Must have at least 2-3 years' experience in automations using Python in ASIC/FPGA development or diag.
- Ideal candidate should have 50% of ASIC/FPGA development experience and 50% Python based automations.
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