Asic Power Architect, Silicon

1 week ago

Bengaluru, Karnataka, India Google Full time

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 5 years of experience in ASIC power management or low power design/methodology.
  • Experience with ASIC low power flows and power management concepts.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with one or more of the following areas: ASIC power modeling and estimation, defining power targets, power management IP and sensors, peak power management/detection/mitigation, inrush current, adaptive clock distribution, techniques for power/voltage domains design, and competitive power analysis.
  • Experience with low power architectures and power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)).
  • Familiarity with PMIC, SMPS, LDO and power delivery networks.

About the job:


Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves.

Your team designs and builds the hardware, software and networking technologies that power all of Google's services.

As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure.

You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing.

Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.


With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities:

  • Define and drive low power solutions for Google SoCs to optimize Power-PerformanceArea (PPA) under peak current and thermal constraints.
  • Create use case workload and data flow models for Day of Use (DoU) power evaluation and drive power and performance optimizations through SoC generations.
  • Define performance/power KPIs and SoC/IPlevel performance/power targets, guide architecture and design to achieve lower power targets to perform power roll ups, and track power throughout the design cycle.
  • Propose and drive power optimizations throughout the design process from concept to mass productization.
  • Drive powerperformance tradeoff analysis for engineering reviews and product roadmap decisions.
Google is proud to be an equal opportunity workplace and is an affirmative action employer.

We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status.

We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law.

If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

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