Apply Now: Principal Design Engineer
1 week ago
- Bachelors in Engineering with 8+ years of experience or Master's with 6+ years of experience.
- Work with analog design team to develop behavioral models for analog blocks using Verilog AMS (Wreal) or SV-RNM constructs. Wok with design verification team in model usage and debugging failures related to models.
- Ensure created model has all major schematic behavior captured for the proper verification of the IP. Work on top level verification bringup of IP with analog blocks as Wreal model.
- Ensure all electrical specifications are validated/checked with respect to test plan or mixed signal Verification plan.
- Support mixed signal verification (Co-Simulation) setup using both command line as well as in Virtuoso.
- Follow and support all the processes as dictated by Cadence and adhering to appropriate checklists at various stages of the design flow.
- Provide regular weekly status, participate in team, project meetings.
- Strong fundamentals in analog circuit concepts/topologies.
- Strong background in mixed signal verification fundamentals, behavioral modelling, verification environment planning & development is a must.
- Ability to read analog schematics and extract related functionality for modelling. Experience in model validation with schematics.
- Strong expertise in modelling especially real number modelling using Verilog-AMS/SV. Some expertise in performance simulation(JTOL) is an added plus
- Experience in creating/contributing towards AMS verification plan .
- Some exposure to functional verification in debugging AMS modelling issues with design and verification engineer.
- Should be process oriented and have exposure to basic scripting/automation
- Good soft skills and experience of working collaboratively in cross site environment.
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