Principal Silicon Front-end Implementation
1 week ago
Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.
Microsoft's mission is to empower every person and every organization on the planet to achieve more.As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals.
Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
We're committed to a diverse and inclusive workplace and strongly encourage applicants from all background and walks of life. Difference makes us better.Responsibilities:
You will be a key link between front-end design and back-end teams.
As a leader in the enablement of quality RTL and collateral file drops to PD, you will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-case PPA.
Strong communication skills will be needed to coordinate with RTL, DFT, CAD and physical design teams.You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail.
You will also be expected to be able to provide crisp status of progress, issues, and risks on the program to the management team.
Looking for strong design team leadership experience.Qualifications:
Required
- Bachelor of Science in Electrical or Computer Engineering
- 15+ years of experience in hardware design
- 10+ years of experience in Synthesis, Timing constraints, Frontend design checks and Power Performance Area (PPA) tradeoffs
- Proficiency in collateral development including timing and synthesis constraints
- Proficiency in frontend design checks including LEC, Lint, Formal Equivalence, and CDC/RDC
- Proficiency in recent synthesis tool capabilities and methods for QoR improvement
- Proficiency in static timing analysis
- Familiarity with RTL and gatelevel power analysis/optimization, UPF, and powerintent verification
- Experience with the projectlevel setup and configuration of 1 or more of the tools related to above disciplines
- Proficiency in translating physical design results into feedback for flow or RTL improvement
- Proficiency in Tcl, Perl, Python, shell programming
Preferred
- Knowledge of full RTL2GDS flow
- Experience in ICC, power integrity analysis, ESD, PV
- Good communication and selfmotivated that can collaborate with larger teams within Microsoft.
- Occasional travel
These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
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