Soc Design Lead
2 weeks ago
This product line will enable a scalable portfolio of ARM based high-end MPUs as emerging trends in AI & analytics, motor control, robotics, HMI and real-time networking are shaping the evolving requirements for applications like autonomous robots, renewable energy, factory and home automation.
The newly formed Sitara MPU team in India will focus on expanding the breadth of TI's portfolio by scaling the execution of MPU devices in 16 FF node and is looking for passionate leaders who can partner to make this a realityResponsibilities :
Lead a So C FE team to own So C integration of a complex multi-processor ARM architecture based So C upto RTM
Manage a high impact FE team and take accountability for their timely deliverables
Collaborate with systems, IP and DV teams to align on feature updates, bug fixes, IP deliverables and ensure timely So C integration releases that cater to Product Requirements
Interact and engage early-on with So C system architect and ensure performance analysis, functional safety requirements, system level use-cases and pin mixing is fully comprehended
Own So C level Component - Debug SS, System clock reset and PM Micro architecture and SC Integration and work closely with architecture team for microarchitecture aspects of the same
Own Chip top creation, Hard macro integration, Pin mux Implementations and work closely with architecture team for microarchitecture details of
Work with backend , DFT team, flow teams to come up with initial So C release
Responsible for RTL releases, Frontend checks for each compile.
Point of contact person to IP team from So C perspective, key member to drive integration reviews and participate in DV reviews to give feedback
Drive complete So C integration, LEC, LINT checks and CDC/RDC analysis to ensure high quality deliverables
Responsible for ensuring power intent of the So C is understood and implemented correctly through Low-Power checks like CLP
Qualifications :
Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 8 to 12 years of experience in IP/So C/subsystem design/integration
Skills :
Experience with integration of So C's with ARM processors, complex bus architectures
Well experienced with analysis and understanding of system level use case scenarios, safety requirements etc
Experience with So C power analysis and power optimization through innovative schemes
- Strong experience with advanced low power techniques and tools such as UPF/CPF, CLP
Experience with industry standard Front End tools like Jasper Gold, Spy Glass, LEC etc
Well experienced with EDA tools such as VCS/Questa/Incisive simulators, Debug tools and Formal verification tools
Good understanding of So C Debug architectures, Design-for-Debug, Design-for-Test will be highly desirable.
Strong written and verbal communication skill with the ability to explain and present complex ideas
Passionate about mentoring and developing people in their careers
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