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Sr VLSI Design Engineer

3 months ago

Bengaluru, Karnataka, India INNOPHASE Full time

INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, Kista, Sweden, and Bangalore, India.

InnoPhase Bangalore is looking for a Senior VLSI Design Engineer to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning.

Job Description:

As Senior VLSI Design Engineer, you will be the key contributor of ORAN SoC product development in the design team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the implementation & verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You also will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 5+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space.

InnoPhase and Synergic Emergence have a co-employment relationship. For over three years, InnoPhase has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and InnoPhase will provide employment, evaluation, and advancement. By outsourcing some HR functions, InnoPhase can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.

Key Responsibilities:

· Participate in SoC specifications reviews and contribute to micro-architecture definitions.

· Front end digital design and implementation – RTL coding, CDC, Lint, and synthesis.

· Develop design constraints and coordinate to debug both functional and DFT test issues.

· Supervise/mentor young engineers for task assignment and ensure productivity and quality.

· Project coordination and status update.

· Help to improve SoC design methodologies and verification quality.

· Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for timely closure of assigned blocks design and implementation issues.

Job Requirements:

· B.E./M.Tech EE/CS with 5 or more years of experience in digital SoC development required.

· Experiences in RTL design using Verilog/System Verilog/VHDL for CPU/control sub-systems (AXI/AHB/APB bus), digital signal processing blocks(FIR filter, FFT/IFFT, NCO).

· Experience of front-end tools (Verilog simulators, linters, clock-domain-crossing checkers).

· Experience in gate level simulation and LEC checking.

· Good understanding on back-end design flow on logic synthesis, constraints, timing analysis, DFT.

· Proven knowledge of System Verilog assertions, checkers, and other design verification techniques.

· Knowledge of languages such as C/C++, Perl, Tcl and Python.

· Good verbal and written communication and presentation skills.

· Team player with ability to collaborate with cross-functional teams to resolve issues effectively.

Desirable Skills:

· RTL coding & simulation in Verilog/System Verilog/VHDL

· Design simulation & checking with Cadence front end tools: Xcelium, SimVision, Jasper RTL Apps

· Python, Perl scripting for verification automation and report generation.

MS Office tools: Excel, power point, Word doc, Visio.