Design Verification Engineer

1 week ago


Bengaluru, Karnataka, India Semi leaf Full time
"Design Verification Engineer" in (Digital ASIC/FPGA verification)

Location :
Bangalore

Experience : 6-10 years

Working Mode :

WFO

Availability :
Immediate to 30 days max

- Experience in Avionics protocols is a plus


Primary Responsibilities :

  • Use highlevel architectural documentation along with algorithm description and implement functions for test bench architecture and design.
  • Develop models in System Verilog to verify design implementation and develop and run scripts and Make files.
  • Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products.
  • Leads reviews of testing and analysis activity to assure compliance to requirements.
  • Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.
  • Leads activities in support of functional verification, simulation, emulation, safety and other technical services/methodologies.
  • Proficient in creating verification plan IPs/Subsystems.
  • Coordinates engineering support throughout the lifecycle of the product.
  • Plans research projects to develop concepts for future product designs to meet projected requirements.
  • Works under minimal direction
Basic Qualifications (Required Skills/Experience) :

  • Experience in identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements.
  • In depth experience in writing Universal Verification Methodology (UVM) sequences and virtual sequences and its concepts like Inheritance, Polymorphism, etc.
  • Experience in using Universal Verification Methodology (UVM): Experience creating drivers, monitors, predictors, and scoreboards.
  • Experience working with selfchecking simulation test bench from scratch for SoCs/ASIC/FPGA.
  • Experience in verification working with internal/external VIPs, its development and evaluation with multiple vendors.
  • In depth understanding in System Verilog language and verification concepts.
  • Work experience using Linux or Unix terminal commands.
  • Experience using scripting languages: Make, Perl, Python, shell scripts, etc.
  • Experience using

Revision Control Systems:
Subversion (SVN), CVS, Git.

Preferred Qualifications (Desired Skills/Experience) :

  • Good Understanding upon designing digital ASIC/FPGA architectural design documents (microarchitecture documents with timing diagrams, detailed design blocks, etc.).
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