Physical Design

1 week ago


Bengaluru, Karnataka, India Capgemini Full time
Job DescriptionSubsystem partitioning, timing budget generations, power planning, Integration of child blocks.
Block level implementation from netlist to GDSII.Handling timing closure of high frequency blocks.
Expertise in signoff closure

Timing with SI and OCV, Power, IR and physical verification at both block and chip level.
Handling blocks of high instance counts

1M instance and above.
Understanding constraints and fixing techniques.
Understanding SI prevention, fixing methodology and implementation.
Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set.
Experience in Design Automation and UNIX system.
Experience in Tcl/ PERL is a plus.
Primary SkillsAble to handle Subsystem PNR activities, Subsystem timing closure and Subsystem physical verificationSecondary SkillsAble to handle Subsystem Synthesis, Subsystem IR drop, Subsystem Lec, Subsystem CLP

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