
Senior/Lead RTL design engineer
4 weeks ago
ACL Digital is Hiring: #RTL_Design_Engineers
Experience: 4–15 Years Experience
Location: Bangalore
Notice Period: Immediate to 30 Days / Serving Notice
Are you passionate about cutting-edge SoC design? ACL Digital is looking for experienced RTL Design Engineers with specialized skills in Synthesis, CDC/RDC/Lint , and Timing Constraints . Join our growing team and work on high-impact projects for global semiconductor leaders
Open Roles & Skill Areas :
RTL Design Engineers with #Synthesis experience:
- Proficient in Cadence Genus (preferred)
- Strong grasp of synthesis methodologies
- Low Power Synthesis using UPF/CPF
- Multi-voltage domain synthesis
- Hierarchical vs flat synthesis
- ECO-friendly RTL techniques
- Advanced retiming & logic restructuring
- Knowledge of LEC
RTL Design Engineers with #CDC / #RDC / #Lint expertise:
- Hands-on with JasperGold / SpyGlass
- Running CDC/RDC checks & parsing reports (XMRs, crossings, waivers)
- Justifying waivers effectively
- Debugging unknowns (X) from reset issues
RTL Design Engineers with #Timing_Constraints experience:
- Deep knowledge of SDC syntax , clock definitions
- I/O timing budgeting
- False & multicycle path management
- STA debugging
- RTL-to-constraint traceability
- Constraint coverage analysis
- Proficient in TCL scripting for automation
Interested Candidates:
Send your CV to
Let's design the future of semiconductors—together
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