FPGA Validation Engineer

3 days ago


Hyderabad, India LeadSoc Technologies Pvt Ltd Full time

Greeting from Leadsoc Technologies Position: Post silicon validation Engineer -HyderabadStrong knowledge in RTL design and implementation Expertise in FPGA design flow and validation Experience with system-level testing and silicon validation Hands-on exposure to debugging (board level & design level) Familiarity with Xilinx / Intel toolchains Understanding of protocols: PCIe, Ethernet, DDR4/5, MemoryExp: 6- 8 yrsNotice: 0-15 days only.RegardsMurali


  • FPGA Validation

    3 weeks ago


    Hyderabad, India ACL Digital Full time

    FPGA Validation EngineerExperience : 4-6 yearsLocation : Hyderabadexperience in Vivado and Vitis &Proficient in Bare metal & C based application.Interested,please share your updated resume to

  • FPGA Validation

    2 weeks ago


    Hyderabad, India ACL Digital Full time

    FPGA Validation Engineer Experience : 4-6 years Location : Hyderabad experience in Vivado and Vitis & Proficient in Bare metal & C based application. Interested,please share your updated resume to

  • FPGA Validation

    3 weeks ago


    Hyderabad, India ACL Digital Full time

    FPGA Validation Engineer Experience : 4-6 years Location : Hyderabad experience in Vivado and Vitis & Proficient in Bare metal & C based application. Interested,please share your updated resume to

  • FPGA Validation

    3 weeks ago


    Hyderabad, India ACL Digital Full time

    FPGA Validation EngineerExperience : 4-6 yearsLocation : Hyderabadexperience in Vivado and Vitis &Proficient in Bare metal & C based application.Interested,please share your updated resume to janagaradha.n@acldigital.com

  • FPGA Validation

    3 weeks ago


    Hyderabad, India ACL Digital Full time

    FPGA Validation EngineerExperience : 4-6 yearsLocation : Hyderabadexperience in Vivado and Vitis &Proficient in Bare metal & C based application.Interested,please share your updated resume to janagaradha.n@acldigital.com

  • FPGA Validation

    3 weeks ago


    Hyderabad, India ACL Digital Full time

    FPGA Validation EngineerExperience : 4-6 yearsLocation : Hyderabadexperience in Vivado and Vitis &Proficient in Bare metal & C based application.Interested,please share your updated resume to janagaradha.n@acldigital.com


  • Hyderabad, India ACL Digital Full time

    Job Description FPGA Validation Engineer Experience : 4-6 years Location : Hyderabad experience in Vivado and Vitis & Proficient in Bare metal & C based application. Interested,please share your updated resume to [Confidential Information]


  • Hyderabad, India ACL Digital Full time

    Exp: 3 to 15 Yrs Location: Hyderabad / Bangalore The core skill set expected from the team is : Exceptional Digital fundamenta ls Hands on experience in System Design with FPGA devices with relevant FPGA EDA too ls Experience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPG As Write high quality code in...


  • Hyderabad, India ACL Digital Full time

    Exp: 3 to 15 Yrs Location: Hyderabad / Bangalore The core skill set expected from the team is : Exceptional Digital fundamenta ls Hands on experience in System Design with FPGA devices with relevant FPGA EDA too ls Experience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPG As Write high quality code in...


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    Exp: 3 to 15 YrsLocation: Hyderabad / BangaloreThe core skill set expected from the team is:Exceptional Digital fundamentalsHands on experience in System Design with FPGA devices with relevant FPGA EDA toolsExperience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPGAsWrite high quality code in Verilog/System Verilog,...