RTL Design Engineering Lead
3 days ago
Hi All,Greetings' from Eximietas Design....We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, and innovative solutions.Key Responsibilities:Define and develop microarchitecture specifications for complex SoC designs.Lead RTL design and implementation using Verilog/SystemVerilog, ensuring optimal performance, power, and area (PPA).Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution.Perform design trade-off analysis to meet functional, performance, and power requirements.Develop and implement design methodologies to improve efficiency and quality.Mentor and guide junior engineers, fostering a culture of innovation and excellence.Participate in design reviews, provide technical leadership, and ensure adherence to project timelines.Qualifications:10+ years of hands-on experience in RTL design and microarchitecture development.Strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis.Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems.Experience with low-power design techniques (e.G., clock gating, power gating, multi-Vt optimization).Familiarity with advanced process nodes and their specific challenges (e.G., finFET, multi-patterning).Strong scripting skills in Tcl, Python, or Perl for automation and flow development.Excellent problem-solving skills and attention to detail.Strong communication and leadership skills.What We Offer:Opportunity to work on cutting-edge semiconductor designs and innovative technologies.Collaborative and inclusive work environment.Competitive compensation and benefits package.Professional growth and development opportunities.📨 Interested?Please share your updated resume with us at: 📧 maruthiprasad.e@eximietas.design.Referrals are greatly appreciated—please feel free to forward this within your network...Best regards,Maruthy PrasaadAssociate VLSI Manager - Talent Acquisition | VisakhapatnamEximietas Designmaruthiprasad.e@eximietas.design+91 8088969910.
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of SoC flows.Primary Skills:VHDL,...
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
-
Rtl design lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of so C flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, Spy Glass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of So C flows.Primary Skills:VHDL,...
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills:...
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills:...
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills:...
-
RTL Design Lead
3 weeks ago
Bengaluru, India Capgemini Engineering Full timeJob Description RTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows....
-
RTL DESIGN ENGINEER-Lead
4 days ago
Bengaluru, Karnataka, India Capgemini Engineering Full time ₹ 12,00,000 - ₹ 36,00,000 per yearJob DescriptionYour RoleAs a SoC Integration Engineer, you will play a key role in the design and integration of System-on-Chip (SoC) components, contributing to the development of high-performance semiconductor solutions. You'll work on RTL coding, verification flows, and integration of IP blocks, ensuring robust and efficient designs that meet industry...
