Digital Verification Engineer

#ACL Digital is hiring: IP Verification Engineer – UVM Verification - We are looking for engineers with strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience. - Hands-on expertise in AXI4, NoC protocols, and multi-master/multi-slave configurations is required. - Experience with DRAM memory controllers, traffic...

#ACL Digital is hiring: IP Verification Engineer – UVM Verification We are looking for engineers with strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience. Hands-on expertise in AXI4, NoC protocols, and multi-master/multi-slave configurations is required. Experience with DRAM memory controllers, traffic...

#ACL Digital is hiring: IP Verification Engineer – UVM Verification- We are looking for engineers with strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience.- Hands-on expertise in AXI4, NoC protocols, and multi-master/multi-slave configurations is required.- Experience with DRAM memory controllers, traffic...

SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob RequirementMust have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.Experience of working on...

SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob RequirementMust have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.Experience of working on...

SSOC Design Verification Engineer - Senior / Lead / Sr. LeadExperience: 5 to 12 YearsLocation: Hyderabad / BangaloreJob RequirementMust have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.Experience of working on...

#ACL Digital is hiring: IP Verification Engineer – UVM VerificationWe are looking for engineers with strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience.Hands-on expertise in AXI4, NoC protocols, and multi-master/multi-slave configurations is required.Experience with DRAM memory controllers, traffic patterns,...

#ACL Digital is hiring: IP Verification Engineer – UVM VerificationWe are looking for engineers with strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience.Hands-on expertise in AXI4, NoC protocols, and multi-master/multi-slave configurations is required.Experience with DRAM memory controllers, traffic patterns,...

Lead Verification Engineer Experience: 7+ years Location: Hyderabad Job Description: Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure Handle regression testing and contribute to verification...

Lead Verification Engineer Experience: 7+ years Location: Hyderabad Job Description: Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure Handle regression testing and contribute to verification...