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Physical Design Lead
4 days ago
Hyderabad, Telangana, India Mulya Technologies Full timeAbout UsWe are a technology consulting company delivering best-in class Chip Design Services.Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skillsApproachWe support a mix of engagement models...
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Physical Design Lead
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Hyderabad, Telangana, India Mulya Technologies Full timeUsWe are a technology consulting company delivering best-in class Chip Design Services.Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skillsApproachWe support a mix of engagement models to...
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Hyderabad, Telangana, India Mulya Technologies Full timeAbout UsWe are a technology consulting company delivering best-in class Chip Design Services.Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skillsApproachWe support a mix of engagement models...
Physical Design Lead
1 month ago
Desired Skills and Experience:
B. Tech. / M. Tech. with 3-10 years of experience in Physical Design The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on an SOC design Should have handled Netlist to GDS II implementation at Chip/partition level for atleast 2-3 designs Hands-on expertise with technology nodes like 28nm, 16nm and below Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip/partition floor planning, placement optimizations, Clock planning and routing. Good understanding of low power implementation techniques and static low power checks IO ring design and bump planning is a plus Being proficient in TCL, Perl scripting is a plus