System-on-Chip Design Engineer

5 days ago

Bengaluru, India ScaleFlux Full time

Title: SoC DesignPosition: Senior SoC/Staff SoC Design Engineer -CPUSSLocation: Bangalore, KA. IndiaCompany and Candidature Brief:Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Sr/Staff SOC Design Engineer responsible for designing complex SOC using ARM architecture. As a Sr/Staff SOC Design Engineer with a focus on ARM Ecosystem Components and Architecture, you will work to understand the internal requirements and complexities of our SOC system and architect the SoC. You will help design the SoC RTL, Integrate IPs and define top level logic. You will also work with verification team to make sure that high quality verification is achieved for first pass success of SoC. You will also participate in architecture/product definition through early involvement in the product life cycle.For a detailed information about us visit the company website:www.scaleflux.comRoles And ResponsibilitiesContribute to SoC architecture for a multi-core ARM SOCDefine SoC micro architecture and designDesign and implementation of CPUSS subsystemWorking closely with the emulation and firmware teams to debug silicon functional issues.Build SoC around key ARM subsystem components and other IPs including various interfacesDesign of clock-reset architecture and RTL implementationIntegration of all IPs into SoCWork with verification team for complete SoC verification, review test plansRTL Simulation and debugSynthesis, Lint, CDC checksAssist in emulation, FPGA, prototyping effortsQualification and Mandatory Skillset Requirements:Minimum BE/BS degree (Masters preferred) in Electrical/Electronic Engineering/VLSI with 5 to 10 years of practical experienceStrong fundamentals in digital ASIC designExpertise in ARM v8 and v9 specifications and their impact to SoC system architectureMultiple project experience with ARM based ecosystem components (A-series ARM Cores, SMMU, GIC, Coresight, NIC and other complex bus interconnects)Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure and multi-core SOC designsExposure to ARM platform architecture specificationsStrong experience with Verilog, SystemVerilog, DC/DC-T based synthesis, constraints development and RTL level checks. Low power methodology knowledge will be a plus.Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART.Capable of working with multiple IP vendors and other teamsExcellent communication and leadership quality to lead design team

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