Lead IC Layout Engineer

Job Title: Analog Layout EngineerLocation: BangaloreDepartment: Engineering / IC DesignJob Title: Analog Layout EngineerLocation: [Your Location]Job Summary:We are seeking a skilled Analog Layout Engineer to join our team. The ideal candidate will be responsible for designing and implementing the physical layout of analog integrated circuits (ICs), ensuring performance, reliability, and manufacturability. You will work closely with circuit designers and verification teams to translate schematics into manufacturable layouts that meet design specifications and industry standards.Key Responsibilities:Develop and optimize the physical layout of analog/mixed-signal ICs including transistors, capacitors, resistors, and interconnects.Collaborate with circuit designers to ensure layouts meet electrical and performance specifications.Perform layout design rule checks (DRC), layout versus schematic (LVS) verification, and parasitic extraction.Address issues related to signal integrity, noise, crosstalk, matching, and device placement.Work with fabrication teams to ensure manufacturability and yield optimization.Support design verification and bring-up activities by providing layout knowledge and debugging assistance.Maintain documentation related to layout designs, design flows, and processes.Keep up to date with industry best practices, tools, and technology trends.Qualifications:Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.Proven experience in analog layout design for CMOS/BiCMOS processes.Strong knowledge of analog device operation and layout challenges (matching, parasitics, noise).Hands-on experience with layout tools such as Cadence Virtuoso Layout Suite or Mentor Graphics Calibre.Familiarity with DRC, LVS, and parasitic extraction tools and processes.Excellent problem-solving and analytical skills.Good communication skills and ability to work in a team environment.We are seeking a skilled Analog Layout Engineer to join our team. The ideal candidate will be responsible for designing and implementing the physical layout of analog integrated circuits (ICs), ensuring performance, reliability, and manufacturability. You will work closely with circuit designers and verification teams to translate schematics into manufacturable layouts that meet design specifications and industry standards.Key Responsibilities:Develop and optimize the physical layout of analog/mixed-signal ICs including transistors, capacitors, resistors, and interconnects.Collaborate with circuit designers to ensure layouts meet electrical and performance specifications.Perform layout design rule checks (DRC), layout versus schematic (LVS) verification, and parasitic extraction.Address issues related to signal integrity, noise, crosstalk, matching, and device placement.Work with fabrication teams to ensure manufacturability and yield optimization.Support design verification and bring-up activities by providing layout knowledge and debugging assistance.Maintain documentation related to layout designs, design flows, and processes.Keep up to date with industry best practices, tools, and technology trends.Qualifications:Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.Proven experience in analog layout design for CMOS/BiCMOS processes.Strong knowledge of analog device operation and layout challenges (matching, parasitics, noise).Hands-on experience with layout tools such as Cadence Virtuoso Layout Suite or Mentor Graphics Calibre.Familiarity with DRC, LVS, and parasitic extraction tools and processes.Excellent problem-solving and analytical skills.Good communication skills and ability to work in a team environment.