Senior RTL Design Engineer

1 week ago


Noida, India TekPillar® Full time

Job Title: Senior RTL Design Engineer Experience: 5 to 8 Years Location: Noida & Ahmedabad We are seeking an experienced Senior RTL Design Engineer with strong expertise in Verilog-based FPGA design and Xilinx toolchains. The ideal candidate will be responsible for end-to-end development—from RTL coding to system integration—on Xilinx Zynq UltraScale+ platforms. Key Responsibilities Design, develop, and verify FPGA modules using Verilog RTL . Perform synthesis, simulation, place & route, and timing closure using Xilinx Vivado . Work extensively on Zynq UltraScale+ platforms and integrate peripheral interfaces such as I2C, SPI, DDR, eMMC, AMBA, PL–PS interfaces . Develop testbenches, run simulations, and ensure design quality and performance. Debug FPGA designs and support hardware bring-up and validation. Collaborate with cross-functional teams (hardware, software, verification) for complete design delivery. Required Skills 5–8 years of solid experience in RTL/FPGA design . Strong proficiency in Verilog , Xilinx Vivado , and FPGA development workflows. Hands-on experience with FPGA architecture, synthesis, constraints, and timing optimization . Practical experience working on Zynq UltraScale+ SoCs and interfacing protocols (I2C, SPI, DDR, eMMC, AXI/AMBA). Good understanding of SoC design concepts and PL-PS integration. Nice to Have Experience in high-speed digital design and multi-gigabit interfaces. Knowledge of HDMI interface , display protocols, or video processing. Familiarity with embedded systems and hardware debugging tools.



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