Principal Memory Design Engineer

Senior/Principal Memory Design Engineer Location: Bangalore, India Experience: 10+ Years About ACL Digital ACL Digital, part of the ALTEN Group , is a next-generation product engineering and semiconductor services company with global presence across 30+ countries. We specialize in ASIC/SoC design, memory IP, verification, embedded systems, automotive, 5G, AI/ML, and cloud solutions , helping clients accelerate innovation and bring cutting-edge products to market faster. Our semiconductor engineering practice is trusted by top-tier semiconductor and system companies worldwide. With state-of-the-art R&D centers and a 20,000+ strong engineering workforce across ALTEN, ACL Digital provides unmatched expertise in advanced node silicon design, memory IP solutions, verification, and silicon bring-up . Role Overview We are looking for a Senior/Principal Memory Design Engineer with deep expertise in high-performance, low-power, and high-density memory IP development for advanced process nodes. This role involves owning architecture-to-silicon delivery of memory solutions and driving technical excellence across global design teams. As a senior leader, you will define architectures, lead circuit and layout design, drive validation, and collaborate with foundries and SoC teams , while mentoring younger engineers and shaping ACL Digital’s memory IP roadmap. Key Responsibilities Memory Architecture & Design Architect, design, and optimize SRAM, ROM, Register Files, CAM, and eDRAM for advanced SoCs. Lead bitcell modeling, sense amplifier design, redundancy schemes, and peripheral circuit design. Deliver low-power, high-speed memory IPs with best-in-class PPA. Implementation & Sign-off Own full flow from schematic design, spice simulations, custom layout guidance, to sign-off . Ensure robustness across PVT corners, aging, IR drop, EM, and reliability constraints. Collaborate with SoC teams for seamless memory integration and closure. Validation & Characterization Define and execute verification methodologies, timing/power characterization, and functional validation . Lead post-silicon bring-up, debug, and yield enhancement programs . Advanced Node Enablement Drive design closure on 7nm, 5nm, and upcoming technology nodes . Partner with foundries for bitcell enablement, technology qualification, and model correlation. Leadership & Mentorship Guide and mentor junior engineers on circuit design best practices and advanced methodologies . Represent ACL Digital in customer discussions, technical reviews, and technology strategy forums . Required Skills & Experience 10+ years in custom memory IP design (SRAM, ROM, CAM, Register Files, eDRAM). Strong command of circuit design (sense amps, wordline/bitline, periphery), variation-aware design, and redundancy/repair schemes . Expertise with Cadence Virtuoso, Synopsys HSPICE, Liberate, Modelsim, and industry-standard EDA tools . Hands-on in timing, power, noise, IR/EM, aging, and reliability analysis . Proven experience in silicon bring-up, validation, and debug . Excellent understanding of SoC integration and memory compiler flows . Good to Have Experience with eFlash, MRAM, RRAM, or other emerging memory technologies . Exposure to machine-learning assisted yield optimization and modeling . Patents, conference papers, or technical leadership in semiconductor forums. Education B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or Microelectronics. Why Join Us? Cutting-edge Projects : Work on next-generation memory IPs for Tier-1 semiconductor customers. Technology Leadership : Be at the forefront of advanced node design (5nm and below) . Global Collaboration : Partner with cross-functional and international teams. Career Growth : Opportunity to grow into Architectural Leadership or Technical Director roles . Innovation-driven Culture : Freedom to innovate, file patents, and contribute to ACL Digital’s IP portfolio.