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Senior Test Architect Lead
4 weeks ago
Job Title: DFT Architect
About the Role:
We are looking for a skilled DFT Architect to lead our team in designing and implementing world-class testability and manufacturability solutions for complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and drive innovative solutions to meet our product requirements.
Main Responsibilities:
- Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
- Lead implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation, MBIST, boundary scan, and IJTAG.
- Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
- Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
- Perform pattern generation, fault simulation, and debug test coverage gaps.
- Own DFT signoff, timing closure, and ATE pattern delivery.
- Support silicon bring-up, test vector validation on ATE, and yield optimization.
- Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
Requirements:
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
- 7+ years of experience in DFT for complex ASIC or SoC designs.
- Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
- Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
- Strong knowledge of RTL design, STA, and synthesis flows.
- Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
Preferred Qualifications:
- Experience with hierarchical DFT and low-power DFT methodologies (UPF).
- Exposure to post-silicon validation and failure analysis.
- Familiarity with safety-critical designs (ISO 26262) and functional safety.
About Us:
- We offer competitive salary, leadership exposure, and fast-track growth opportunities.
- Collaborate with top-tier engineers and global semiconductor leaders.
- Contribute to high-performance, next-gen SoCs and ASICs.
