ASIC RTL Design Engineer
3 weeks ago
ASIC Design Engineer
We are seeking a skilled ASIC Design Engineer with a solid background in digital design, RTL coding, and ASIC development. The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance ASICs, with a strong focus on SystemVerilog or VHDL. This role will involve taking designs from concept to tape-out, working in a collaborative environment with cross-functional teams, and ensuring that designs meet performance, area, and power requirements.
Key Responsibilities:
- Digital RTL Design: Design and implement high-performance RTL using SystemVerilog or VHDL for complex ASIC designs.
- Architecture Development: Contribute to the design and specification of digital architectures and system-level components, including processors, memory controllers, and high-speed interfaces.
- Synthesis & Optimization: Perform logic synthesis, timing analysis, and optimize for area, power, and performance (PPA) during the design process.
- Design Integration: Integrate and interface complex digital blocks into a cohesive system-on-chip (SoC) or ASIC.
- Verification: Collaborate with the verification team to develop testbenches, perform functional simulation, and ensure correctness and robustness of designs.
- Timing Closure: Work on timing closure for your designs using static timing analysis (STA) tools and ensure all designs meet required timing constraints.
- Design for Low Power: Implement low-power design techniques, such as clock gating, power gating, and dynamic voltage scaling.
- Collaboration: Work closely with cross-functional teams, including physical design, verification, software, and quality assurance teams, to ensure successful integration and deployment of ASIC designs.
- Documentation: Produce detailed design documentation, including design specifications, test plans, and simulation results, and track progress against development milestones.
- Debugging & Optimization: Use simulation tools and hardware debugging techniques to troubleshoot design issues and improve performance, timing, and power.
Required Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 4+ years of hands-on experience in ASIC design and RTL development.
- Expertise in RTL coding using SystemVerilog or VHDL.
- In-depth knowledge of digital design principles, including finite state machines (FSMs), timing analysis, clocking schemes, and synchronous design.
- Familiarity with ASIC design flow, including synthesis, place and route, timing closure, and power optimization.
- Experience with simulation tools like ModelSim, VCS, or Questa for functional verification.
- Knowledge of static timing analysis (STA) and timing closure techniques.
- Strong understanding of power analysis and implementation of low-power design methodologies.
- Experience with hardware debugging tools (e.G., logic analyzers, oscilloscopes, protocol analyzers) for bringing up prototypes.
- Excellent communication skills and the ability to collaborate effectively with cross-functional teams.
Experience: 4 to 10 Years
Location: Bangalore / Hyderabad
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