Design Engineer I

1 month ago

Bengaluru, India Cadence Full time

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Job Title: Design Engineer I ( Layout Design )

Location: Noida / Bangalore

Experience: 2-5 Years

Profile to kmadhup@cadence.com

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer successMultiple avenues of learning and development available for employees to explore as per their specific requirement and interestsYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.
Job Summary:

Drives development of products and technologies and has material responsibility for the success of that product/technology.

Job responsibilities:

Custom layout design for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts.

 Perform physical verifications like DRC/LVS/Reliability and fixing violations Lead custom layout efforts for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts. Would be required to lead/mentor a small team of engineers towards a successful IP delivery. Perform physical verifications like DRC/LVS/Reliability and fixing violations
Experience and Technical Skills required

Hands on layout design experience in various analog IP like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.

 Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Knowledge of various analog layout techniques like matching, shielding etc., Good understanding of DSM technology methodology, issues etc., Having worked on latest technology nodes, 28nm and below, is desired. Must have good communication skills and should be team player. Scripting and automation experience is a plus. Hands on layout experience in various analog IP like High speed Analog (Serdes), Data converters, power management and PLL etc. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario. Good understanding of DSM technology methodology, issues etc., Having worked on latest technology nodes, 28nm and below, is desired. Must have good communication skills and should be team player. Scripting and automation experience is a plus. Good communication skills, documentation and presentation skills. Strong analytical and problem-solving skills.
Education Level: Bachelor's Degree / Master's Degree (MSEE Preferred).


K Madhu Prasad ( Madhu Reddy ) |

K Madhu Prasad kmadhup@cadence.com

Staffing Group

www.cadence.com

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