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Staff Engineer, ASIC Digital Design
3 months ago
Job DescriptionWork on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standardsIP/design blocks/Firmware Specification study and build/update verification plans as well as the test casesBuild/update functional verification environments to execute the test plansImplement checkers, assertions, random test generators, high level transactional models and bus functional models (BFMs) as per the verification plan needsPerforming simulation, random and direct stimulus development and coverage reviewWork closely with digital designers for debug and achieve the desired coverageRequirementsB.Tech/M.Tech with 3+ years of relevant experienceUnderstanding of functional verification flow with experience on industry standard development and verification tools and methodologies VMM, OVM/UVM and System VerilogExperience with System Verilog Assertions, code and functional coverage implementation and reviewScripting and automation using TCL/PERL/PythonExcellent debug and diagnostic skillsOur Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of digital, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
