Physical Design

1 week ago

Bengaluru, India Eximietas Design Full time

Hi All,


Eximietas Hiring Senior Synthesis/Constraints.

Experience: 8+ Years.

Location: Bengaluru.


Block / Subsystem / Partition / Full chip.

• Role: Synthesis and Timing Constraint Engineer.

• EDA Tool: Cadence Genus & Fishtail.

• Node: TSMC 3nm / 5nm.

• UPF Implementation hands-on is must.

• Synthesis PPA optmimization, Hierarchical partition synthesis, Lint, Sanity Checks.

• Timing constraints generation and validation.

• Tcl, Perl, Python Scripting mandatory.


Interested Candidates please start sharing your resumes: maruthiprasad.e@eximietas.design

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