Principal SoC Microarchitecture and IP Logic Design Engineer

4 weeks ago


Greater Hyderabad Area, India Mulya Technologies Full time

Principal /Senior Staff SoC Microarchitecture and IP Logic Design Engineer

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad

A US based well-funded product-based startup looking for Highly talented ASIC / RTL / Logic Design Engineers for the following roles.

  1. we are looking for candidates with Arm IP background like: CHI, CMN, Arm CPUs, etc

Responsibilities

  • Work in designing and integrating a high-performance System on Chip
  • Architectural exploration for power, performance and area efficient SoCs
  • Microarchitecture development for PPA efficiency and creating microarchitecture specification documents
  • Perform efficient RTL coding in Verilog or System Verilog towards IP development, and integrate SoC RTL modules in building large systems
  • Make external sourcing versus custom design decisions for various SoC modules
  • Collaborate with performance analysis team to design, correlate and enhance performance metrics
  • Collaborate with pre-silicon verification, emulation and post silicon validation in developing validation infrastructure and making sure design is functionally correct
  • Collaborate with physical design team in synthesis, place and route planning, and to make sure design meets area and frequency requirements
  • Work with cross-functional engineering teams to ensure the design is of high quality

Requirements

  • Master’s, PhD or bachelor’s degree in relevant subject area
  • Thorough knowledge of high-performance CPU, GPU or heterogenous compute systems
  • Prior experience designing and integrating high performance Arm, x86 or RISCV SoCs
  • Prior experience with IP development and RTL integration of SoC components like Interconnects, memory controllers, IO controllers like PCIe/CXL, etc
  • Proficiency in Verilog or System Verilog coding, and ability to identify PPA efficiency enhancements in RTL
  • Understanding of high performance and low power microarchitecture techniques and logic design principles
  • Experience with front end ASIC design EDA tools like simulators, waveform debuggers, IDEs, etc


Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"



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