DFT Egnieer/DFT lead

3 weeks ago


Bengaluru, India Spot Your Leaders & Consulting Full time

Lead Role: (Mandates).


  • Top Level / SOC Level Hierarchical DFT Implementation.
  • Scan Insertion Including DRC Debug, Compression.
  • ATPG Pattern Generation and validation.
  • Experience in Post silicon debug.
  • Timing & No Timing Simulation.
  • MBIST / JTAG / IJTAG
  • Tools : Tetramax-Synopsys, Mentor- Tessent


Mid-Range (4 to 7 years).


  • Scan Insertion Including DRC Debug, Compression.
  • Hierarchical DFT Implementation experience
  • ATPG Pattern Generation and validation.
  • Experience in Post silicon debug.
  • MBIST Validation
  • SMS (Star Memory System)
  • Stuck-at Fault and Transition Fault schemes.
  • IDDQ / Small Delay Defect.
  • Tools : Tetramax-Synopsys, Mentor- Tessent


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