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AMS Verification Engineer
5 months ago
Job Title :Senior Engineer - AMS Verification
Job Description
BE/B.Tech in ECE /M.Tech in VLSI with 3 to 9 years experience in Analog Mixed Signal Verification
• Good experience in Verilog AMS, Verilog-A, WREAL, modelling of Analog blocks
• Good experience in Analog Mixed Signal verification simulation tools
• Good experience in System Verilog, UVM methodologies
• Able to train the team members and guide the team in resolving issues
• Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch.
• Good to have Gate level netlist simulation
• Python, Perl, Shell scripting is added advantage.
• Good communication and documentation skills
Mandatory Skills
System Verilog,Scripting,Verilog,Analog Modeling,Verification and Validation,Verilog-A,AMS Verification,Python (Programming Language)
Location: Hyderabad
Notice period - Immediate to maximum 45 days preferred