Design Verification Engineer
1 month ago
Job Location: Bangalore/Hyderabad.
Exp.-4+yrs
Notice Period less than 30days.
- System Verilog based UVM Functional verification, System C/C++ based functional verification. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.
- Knowledge of USB/PCIe/Ethernet is a plus.
Regards,
Sneha
ACL Digital
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