Analog Design Engineer

3 weeks ago

Hyderabad, India 7hillsTS Full time

Job Title :

Analog Mixed-Signal (AMS) Layout Engineer


Experience Required:

3 to 5 years in custom analog and mixed-signal IC layout design.


Location : Hyderabad


Job Summary:

We are looking for an AMS Layout Engineer with strong experience in full-custom analog and mixed-signal layout design. The role involves working on layout of critical AMS blocks such as OpAmps, PLLs, ADCs, DACs, LDOs, SerDes PHY, and IO circuits, ensuring compliance with foundry rules, parasitic optimization, and robust silicon performance.


Key Responsibilities:

  • Perform full-custom layout of analog and mixed-signal circuits at block and top level.
  • Work closely with analog designers to translate schematics into optimized layouts.
  • Ensure DRC, LVS, ERC, and ANT clean layouts.
  • Optimize for area, matching, symmetry, shielding, and signal integrity.
  • Handle device matching techniques (common-centroid, interdigitation, guard rings).
  • Perform parasitic extraction (PEX) and support designers with post-layout simulations.
  • Manage PVT variation and layout-dependent effects (LDE).
  • Collaborate with physical verification teams to resolve sign-off issues.
  • Support SoC integration teams for mixed-signal IP integration at chip level.
  • Maintain thorough documentation of layout guidelines and best practices.


Required Skills & Qualifications:

  • 3–5 years of experience in AMS custom layout design.
  • Proficiency with EDA tools:
  • Cadence Virtuoso (XL/GXL)
  • Mentor Calibre / Synopsys ICV (for DRC/LVS/PEX)
  • Strong knowledge of layout techniques for:
  • Analog blocks (OpAmps, Bandgaps, LDOs, Comparators)
  • Mixed-signal IPs (PLLs, ADCs, DACs, SerDes)
  • High-speed & low-power designs
  • Experience in parasitic extraction flows (QRC, StarRC, Calibre xRC).
  • Knowledge of CMOS device physics and layout-dependent effects.
  • Familiarity with ESD protection and IO layout.
  • Understanding of reliability checks (EM/IR, latch-up prevention).
  • Strong communication and teamwork skills to work with analog designers and verification engineers.


Preferred Skills:

  • Experience in FinFET / advanced nodes (16nm, 7nm, 5nm, etc.).
  • Exposure to high-voltage analog layout (power management ICs).
  • Knowledge of layout automation / scripting (SKILL, Python, TCL).
  • Prior tapeout experience with AMS IP blocks or SoCs.


Educational Qualification:

  • B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.

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