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Design Verification Engineer
2 months ago
job details:
Work with floorplan and physical design engineers to drive physical verification convergence.
Should be proficient in DRC and LVS analysis at advanced nodes like TSMC5 or below.
Good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred.
Working knowledge on full chip phyV will be added advantage.
Understanding on multi voltage regions will be preferred.
Experience: Minimum 4- 7 yrs experience on Physical Verification exclusively.
Tools: Expertise in Calibre and Innovus
Scripting will be preferred.
Scripting inside Calibre tool will be added asset