Senior RTL Design Engineer
1 month ago
Senior Front-End SoC/ASIC Design Engineer
Location: Bangalore
We are an innovative enterprise that designs, develops and delivers System-on-Chip solutions to customers worldwide. The company is focused on AR/VR, ADAS, imaging, networking, data storage and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We. is headquartered in Yokohama, and has offices in Japan, Asia, United States and Europe to lead its product development and sales activities. , a wholly owned subsidiary of
We are seeking a Front-End SoC/ASIC Design Engineer for our SoC business unit.
Responsibilities Include but are not Limited to:
· Support customer’s design through all phases of ASIC execution
· Ensure designs meet product Performance-Power-Area-Schedule requirements. Tasks may include Architecture / micro-Architecture; Logic Design; RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up.
· Ensure deadlines for project milestones are met while maintaining quality.
· Work effectively with internal and external (including customer and vendors) teams (Note:we teams located globally).
· Display a results-focused attitude and accomplish Company/Team-goals.
Required/Desired Qualifications:
· Bachelor’s Degree in EE or similar degree.
· 7-10 years of professional design experience, provided the work experience is solid micro-architecture and front-end design.
· Hands-on ASIC front-end design, ideally in design services environments (product backgrounds acceptable).
· Skills Required – Micro-architecture at module/sub-system/chip-level; digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings; integration of IPs/modules/sub-systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support.
· Technical document writing skill
· Teamwork, dedication, collaborative, strong communications, and interpersonal skills.
· Ability to meet stringent deadlines and project timelines.
· Skills Strongly Desired – SoC Architecture experience. Experience and domain-knowledge in at least 2-3 of these: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine-learning / AI; FPGA.
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
Email: muday_bhaskar@yahoo.com
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