Design Verification Engineer

3 weeks ago

Bengaluru, India ACL Digital Full time

Experience: 4-5 YearsLocation: Bangalore/HyderabadEducation: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/ElectronicsRoles and ResponsibilitiesVerilog, System verilog, UVMVHDL, UVVMSimulator exposure with VCS, Questa, XceliumProficient in simulation and HW languagesShould be able to interpret various LRMs and comply with semantics and testcase creation.Share the profiles to raksha.k@acldigital.com.

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