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Staff engineer
1 week ago
Bangalore
Top10 Semiconductor Organization in the world
Staff engineer , ASIC Design Verification
Job Description
- To be part of a highly skilled and challenging high speed DDR & ONFI PHY design team working on the newest technology nodes
- Responsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.
- Leading, mentoring and coaching junior team members
- Work closely with Digital and Analog designers
Skills Required
- Good experience of logic simulation, UVM environment and testbench creation
- Experience with timing simulation and debug
- Experience with RTL debugging, score boarding and code coverage analysis
- Working knowledge of CDC and Lint
- Exposure to verification of complex high speed PHY and/or complex AMS IPs
- Understanding of DDR/LPDDR JEDEC or NAND ONFI and DFI protocols
- Sound knowledge of Verilog and System Verilog languages
- Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A
- M.S./M.Tech, BS/BE (Electronics)
Experience Required: 7+ Years
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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