Lead UVM Verification

2 weeks ago

Bengaluru, India Centum T&S Full time

Job description


CENTUM T&S, headquartered in France, is a business unit of Centum Electronics Group (Around 1000Cr turnover organization) offering a wide range of electronic and embedded systems design engineering services to international customers to help them realize complex products and sub systems. It includes design, development, qualification, value engineering, testbench design & manufacturing and many more services. Centum T&S has established its India operations in North Bengaluru, known as Centum T&S Pvt Ltd (CTS), formerly known as Centum Adeneo India Pvt Ltd. CTS is working with many top companies like Airbus, Thales, Hitachi Energy, GE, ABB, DANA, Alstom, etc., CTS has ambitious plans to grow to about 250 people by December 2024, delivering best-in-class electronics systems, designed to global standards based on customer specifications

The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager.


What You do


  • Work on cutting edge FPGA based verification environment creation which is a mix of :

SV, UVM

  • System Verilog Models and TB expertise
  • IP verification expertise
  • Working on debug skills and problem solving attitude.
  • Experience of working in complex test-bench/model in UVM - System Verilog
  • Reviewing and assessing proposed design changes from a verification complexity point of view
  • Architecting verification IP and full verification environments
  • Investigating and scripting new verification flows and optimizing existing ones
  • Analysis of data from simulation runs to drive efficient bug discovery and debug
  • Developing methodology and deploying within the group and having full ownership of verification closure and mentoring other members of the team.
  • Close collaboration with other FPGA engineering teams leading to high quality verification environment/RTL deliverables that works well in a complete system


Key values, beliefs, and attitudes

  • Results-orientation: Focus on Customers, provide quality deliverables on time, within estimated effort with high quality
  • Characteristics for a design engineering services business: establish trust, responsive to change/adaptability; learn continuously, proactive, positive & joyful.


Who You Are?

  • You can demonstrate experience in working with constrained-random verification including ownership of a suitably complex verification environment.
  • Experience of architecting and implementing functional verification environments for complex IP.
  • Experience developing re-usable and scalable code whilst having good knowledge of UVM.
  • Strong scripting skills - being able to develop scripting to support new flows.
  • Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
  • You are familiar with the tools and processes for developing test benches and finishing all aspects of the verification process.
  • Strong communication skills and ability to work well as part of a team.
  • Dedicated with a focused approach to problem analysis and solving.
  • Strong experience in planning and estimation.
  • Team leadership and mentoring experience
  • Multiprocessing microarchitecture experience including knowledge of bus protocols (e.g. AXI4 Stream, AXI4 Lite, High Speed 100G Ethernet)
  • Hands on experience with AMD Ultrascale+ MPSoC architecture
  • Experience in Formal Verification test benches is a plus.

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