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Senior Physical Design Engineer

3 months ago

Greater Bengaluru Area, India Mulya Technologies Full time

A Large Service and Solutions Organization with Revenue over 500 Million USD

Location; Bangalore


Job Area

Hardware Engineering


Job Description Summary


General Summary:

Join the us as a Physical Design Engineer for the most cutting-edge work. we assist our clients in developing their next generation flagship product lines (mobile devices, complex routers/switches, consumer products, storage, microprocessor, graphics

processors etc.). This includes developing cutting edge technologies that are key and rare in the industry. We offer a fun, creative and flexible work environment.


As a Physical Design Engineer, you will work with different teams like microarchitecture, PCIe, CLX, SOC, GPU, CPU, Defence teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.


Title :: Physical Design Engineer ( Low Power )

Location :: Bengaluru, Karnataka, India


Job Description ::

What are the top non-negotiable skill sets required for this role?

• Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies

• Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.

• Experience working with most EDA tools like Fusion Compiler/DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre

Duties:

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.

• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution

• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design


Must Have:

• 5 years of relevant physical design experience

• Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs

• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.

• Experience in Block-level and Full-chip floor-planning, power grid planning

• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.

• Experience with Python, TCL, Perl programming

Wish List/ Nice to Have:

• MSEE/CS or equivalent experience

Education

• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science

• Master's Degree preferred but not required


Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com