CPU Verification Engineer
2 months ago
A Fortune 100 Organization
Location: Bangalore
Senior Design Verification Engineer
Role & Responsibilities :
· As a Functional verification engineer, you will be working on server CPUs/SOC or ASICs used in servers.
· Leading the development of the verification environment, testbenches and writing testcases.
· Develop skills in Functional verification tools and methodologies.
· Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design
· Work with development team to ensure coverage criteria is met.
Required Professional and Technical Expertise :
· 5+ years of experience in Functional Verification of CPUS or ASICs.
· Minimum 3+ years of experience in any of the following
a. Computer architecture knowledge, CPU core design specifications, instruction set architecture and logic verification.
b. Core architecture/micro-architecture verification
c. Multi-processor cache coherency, Memory subsystem verification.
d. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc
e. AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification.
f. Gate level simulation and emulation.
· Track record in leading team.
· Clock domain crossing and reset domain crossing verification
· Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/
· Knowledge of HDLs (Verilog, VHDL)
· Developed test-plans and test strategies for IP/unit/block level verification.
· Good object-oriented programming skills in C/C++, scripting languages like Python/Perl.
· Worked on multiple levels of verification (unit/element/sub-system/system level)
· Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow
· Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails
· Experience in driving verification coverage closure.
Additional skill
· Stress testing and ability to identify corner case scenarios.
· Knowledge of high-speed SERDES and PHY Verification
· Good understanding of computer system architecture and microarchitecture.
· Knowledge in IP Integration and SoC level verification.
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
Email: muday_bhaskar@yahoo.com
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