Principal Engineer

6 months ago


Bengaluru, India Microchip Technology Full time

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

Visit our page to see what exciting opportunities and company await

Job Description:

We are seeking a highly motivated Synthesis and STA Engineer to join our team. The successful candidate will be responsible for performing Synthesis and STA timing closure for our cutting-edge microchip designs. The ideal candidate will have a strong background in Synthesis STA and experience with industry-standard EDA tools.

Responsibilities:

-Perform Synthesis and STA timing closure for multi-million hierarchical complex microchip designs.

-Lead and drive team members to complete Implementation activities.

-Complete timing closure for blocks & top level in advanced nodes.

-Develop constraints and perform post-layout timing closure.

-Perform CLP and LEC for both full chip and block level.

-Experience on UPF/CPF would be an added advantage.

-Collaborate with cross-functional teams to ensure timely delivery of high-quality designs.

-Optimize design performance through timing closure and power optimization.

-Develop and maintain design constraints and timing models.

-Analyze and debug timing issues.

-Inserting DFT logic for both block and top level.

Requirements/Qualifications:

-Bachelor's or master’s degree in electronics engineering or related field

-8+ years of experience in Synthesis STA

-Experience with industry-standard EDA tools such as Synopsys, Cadence, and Mentor Graphics like Genus, DC compiler, Tempus, Primetime.

-Strong understanding of timing closure and power optimization techniques

-Excellent analytical and problem-solving skills

-Strong communication and collaboration skills

Travel Time:

0% - 25%
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