Staff Engineer, Design Verification Engineering

6 months ago

Bengaluru, India Analog Devices Full time

As part of the DBU ASIC team, we are looking for passionate and self-motivated DV Engineer that will work with a multi-functional engineering team to develop a range of block, subsystem and system solutions for digital processing subsystems. You will be intimately involved in pushing the envelope of the various DV technologies. You will be working on driving real revenue growth for ADI working on the next generation of Intelligence at the Edge products. You will be working in a highly dynamic environment with a lot of custom designs, interacting with geographically diverse teams.

Responsibilities

This position will involve many of the following tasks.

Verification of complex microprocessor designs, neural nets and high-speed peripherals using leading edge verification methodologies. UVM testbench architecture development Defining testplans, tests and verification methodology for block / subsystem and chip-level verification. Working with the design team in generating and reviewing testplans and closure of code and functional coverage Working with other verification team disciplines like emulation, FPGA and Firmware teams to determine correct functionality. Innovating verification solutions to hit deliverable schedules. The chance to be exposed to and learn state of the art verification techniques such as formal, emulation, portable stimulus and virtual platforms.

Qualifications

The successful candidate will have

Bachelor's or Master's degree, in Engineering (Electronic Engineering) or equivalent with 8+ years verification, or related work experience. Hands on experience in developing, updating and debugging of Verilog, SV-UVM , SOC level testbenches is a must. Experience in closing the verification of block, subsystem level verification using industry standard metrics like code and functional coverage is a must. Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques with System Verilog Indepth knowledge of SV-UVM and debugging of testbenches is a must. Assertion and formal knowledge is an advantage. Knowledge of microprocessor cores such as ARM, RISC-V, Tensilica , Neural Network, GPU Cores is a plus. System Verilog, C/C++, System C, TCL/Python/shell-scripting Proven track record of quick to adopt new technologies with good problem-solving skills Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. AMBA BUS protocols like AHB, APB. AXI is a must. Knowledge of UART, SPI, I2C, I3C, NVM/OTP, E-fuse, Ethernet, Audio (I2S, TDM, SPDIF), DSP, USB, Image Processing, JTAG, Debug Trace will be an added advantage. GLS, UPF, Low Power Simulations. Tool Knowledge of different simulators is desirable. Matlab modelling is desirable. Mentorship skills for fresh graduates and junior engineers. Proficiency in the technical management of large DV teams is a must. A good working knowledge of different DV methodologies like PSS, formal, Emulation is desirable. Should be able to interact with diverse disciplines like FPGA, Software, Virtual Prototyping. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days

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