Physical Design Engineer III, Silicon

4 days ago

Bengaluru, Karnataka, India Google Full time ₹ 20,00,000 - ₹ 25,00,000 per year
Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience with programming languages such as Perl, Python, or TCL.
  • Experience in managing block physical implementation and Quality of Results (QoR).
  • Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs.
Preferred Qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with computer architecture.
  • Experience with constraints, synthesis or Clock Tree Synthesis (CTS).
  • Experience with 7/5/3/2nm node.
  • Knowledge of Register-Transfer Level to Graphic Data System II (RTL to GDSII) in innovus or cadence tools.
  • Knowledge of Electromigration IR Drop (EMIR), Static Timing Analysis (STA), Photon Doppler Velocimetry (PDV), Logic Equivalence Check (LEC) and VC Low Power (VCLP) flows.
About The JobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities
  • Use investigative and simulation techniques to ensure Performance, Power, and Area (PPA) is within defined requirements.
  • Collaborate with cross-functional teams to debug failures or performance shortfalls from program goals in lab or simulation.
  • Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
  • Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign-off or implementation domain to enable cross-functional teams to build and deliver blocks that are rectified by construction and ease convergence efforts.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.

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