Jd for senior physical design requirements
1 month ago
About the Role - PD - Director
Responsibilities -
Minimum 15+ Years of experience So C Physical Design.
Have working experience in advanced Fin FET node designs 7nm/5nm/3nm.
Experience with Cadence/Synopsys Pn R/STA tools and Calibre; good scripting/automation skills is a must.
Work hands-on to solve critical design and execution issues related to physical verification/implementation and sign-off.
Qualifications - Education details
Location - Hyderabad & Bangalore
Required Skills -
Strong hands-on experience with Chip Level / Sub-chip level floor planning.
Performing floor-planning and routing studies and implementation at block and full-chip level.
Push down the top-level floorplan and clock to Partition.
Partition, pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps.
Closely working with Package team and reaching Die file milestones.
Interested candidates, Kindly reach me +919900927620 OR mail me
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