Sr staff formal verification engineer
2 weeks ago
Formal Verification Application Engineering, Staff Engineer
Job Responsibilities
Promote adoption of Synopsys Formal Verification Apps to new Customers by delivering presentations and demos
Work with Customers to understand their flow requirements and map them to solutions available within Synopsys Formal Verification Apps
Collaborate with Rn D and Product marketing to develop new flows/functionalities
Define formal verification flows and methodologies to improve customer productivity
Develop custom scripts, create work arounds, and provide a quick solution while the features are being enhanced.
Own the customer relationship, i.e. work with R&D and other teams to make sure customer requirements are well understood and track the development of features required by the customer
Job Requirements
EE graduate from reputed school. Post-graduates are preferred
6-10 yrs. of industry experience in RTL design or verification engineers involved in deploying verification methodology using simulation-based technologies
Exposure to assertion-based verification (in simulation) is preferred and experience with formal verification tool is desirable but not mandatory
Managing verification responsibility for hardware designs, verification consulting experience is desirable
Good understanding of hardware design (Verilog/VHDL) and micro-architecture.
Exceptional understanding of Unix/Linux automation shell (bash, csh) and scripting (Tcl, Perl, Python)
Great oral and written communication skills.
Ability to work autonomously
Expertise in one or more of scripting/programming languages like TCL/Python/Perl/SKILL
Expertise in one or more areas like:
Formal Property Verification testbench development
Good understanding floating point arithmetic operations, C/C++ and IEEE math libraries
Understanding of Security architecture and verification
Automotive Safety (Fu Sa) verification
Getting closure and verification signoff with formal
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