Senior Design Verification Engineer

4 weeks ago

delhi, India Texas Instruments Full time
Who are we and what do we do
The Custom product business is delivering industry leading custom IC system solutions including display and touch power products, camera PMICs, charger power products, power switches/muxes, Laser drivers, High speed communication interfaces. Our solutions integrate signal chain and power components, that enable TI customers to differentiate their next-gen products in the personal electronics domain. This is a great opportunity to be part of the best custom semiconductor team in the world.
What will you be doing in this role? (Responsibilities)
Responsible for driving verification strategy, creating Test Plans and developing Test Benches for Chip Top.
Must have Grounds up development of the DV environment based on the system requirements
Must have experience with GLS setup.
Chip Top Level DV signoff using FV(Formal verification)
Or
Top Level DV signoff using SV & UVM:
Code/develop UVM components like agent, driver, monitor and score board
Define and meet all functional coverage goals
Achieve 100% code coverage (Block, expression, FSM) in IP DV
Tools: Vmanager, vplan knowledge is a plus.
Able to automate using perl or python
Post silicon Activities:
Understanding the generation of functional patterns for ATE
Interacting with Product Engineering team to characterize IO timing on Silicon by providing AC characterization TDLs.
Interacting with Application Engineering team to ensure successful use of products in the marketplace and support customer applications debug/analysis.
What do we expect from you? (Mini Qualifications)
Excellent debugging and problem solving skill
Effective communication skills to interact with all stakeholders.
Thorough knowledge of standard protocols. Ex: I2C, SPI, UART
Team and People Skills: The candidate should have good people skills to work closely with the architecture and product apps team.
Exposure to AMS will be added advantages
Preferred Skills/ Experience
4-10 years of experience in IP DV, SoC DV and post-silicon debug
Experience in Cadence simulation tools

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