Senior/Lead ASIC/IP Verification Engineers

3 weeks ago

bangalore, India Synopsys Inc Full time
We are looking for experienced Senior/Lead/Architect PCIE Verification Engineers for our Bangalore & Noida VIP team. Does this sound like a good role for you?
- Staff/Sr Staff/Principal Engineers (R&D Engineering)
- Experience : 4yrs to 15 years (multiple level roles)
- Location: Bangalore & Noida
- Associated with SOC/IP Verification especially using industry-standard protocols & methodology
- Languages: Hands-on experience with System Verilog & Verilog. Should have a good understanding of Object Oriented Programming.
- Should have experience on PCIe protocol preferably the latest specifications like PCIe Gen6.
- Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies.
- Job responsibilities:
- Able to contribute to the development of the VIP
- Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective.
- Should be able to define Testplan for the PCIe specification features, develop sequences and testcases, ensure validation completeness through regression stability and coverage convergence.
- Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective
Please share your updated CV to or refer who would like to explore this opportunity.
- Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

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