Senior ASIC Design Verification Specialist

2 days ago

Delhi, Delhi, India beBeeVerification Full time ₹ 5,00,000 - ₹ 8,00,000

The Role:

We are seeking a skilled Design Verification Engineer to join our team. The successful candidate will have a passion for modern, complex processor architecture, digital design, and verification in general.

Key Responsibilities:

  • Collaborate with the Architecture and Design teams to understand verification asks
  • Develop detailed test plans based on architectural specifications
  • Have a good understanding of SoC design and architecture
  • 10+ years of experience in Design Verification with strong Verilog, System Verilog, C, and UVM/OVM knowledge
  • Candidate should be able to develop Testbench. Thorough understanding of verification environments including stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions.
  • Own the DV sign-off and ensure a bug-free design
  • Work with the post-silicon team on debug support and to help root-cause any failures
  • Have worked on wireless protocol design verification
  • Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow
  • Exposure to DEBUG concepts such as JTAG etc
  • Comfortable with VCS/Verdi and excellent debug skills
  • Logical in thinking and ability to gel well within a team
  • Good communication skills
  • Continuously drive methodology improvements to improve efficiency
  • Mentor junior engineers to build a high-performing team

PREFERRED EXPERIENCE:

  • Proficient in SoC/sub-system/IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches
  • Experienced with Verilog, System Verilog, C, and C++
  • Worked on High Speed Interfaces like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol
  • Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
  • Scripting language experience: Perl, Python, Makefile, shell preferred

Benefits:

  • Opportunity to work with a talented team of engineers
  • Professional growth and development opportunities
  • A competitive compensation package

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