Senior ASIC Design Engineer
1 day ago
About the Role
Lattice Semiconductor is a leading provider of programmable logic solutions that are changing the industry. We are seeking an experienced Senior ASIC Design Engineer to join our team in Pune, India.
Job Summary
The successful candidate will be responsible for implementing RTL to GDSII flow for complex ASIC design, with a focus on power, performance, and area optimization. The role will involve collaborating with RTL, DFT, verification, and full chip teams to ensure robust design implementation.
Responsibilities and Accountabilities
- Serve as a key contributor to FPGA design efforts
- Drive physical design closure of key ASIC blocks and full chip, achieving best-in-class methodologies for power, performance, and area
- Ensure design quality through all physical design quality checks and signoff
- Develop strong relationships with worldwide teams
- Mentor and develop strong partners and colleagues
- Occasional travel as needed
Qualifications and Requirements
- BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science, or equivalent
- 5+ years of experience in driving physical design activities of ASIC blocks and full chip
- Experience working with industry-standard physical design tools, including Innovus, Genus, Tempus, Voltus, Calibre, and Conformal
- Independent worker with demonstrated problem-solving abilities
- Proven ability to work with multiple groups across different sites and time zones
Salary and Benefits
The estimated salary for this position is ₹20-25 lakhs per annum, depending on experience. Lattice Semiconductor offers a competitive benefits package, including health insurance, retirement savings plan, and paid time off.
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