Highly Experienced Analog Layout Engineer for Advanced DRAM Development
1 week ago
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. Our vision is to transform how the world uses information to enrich life for all.
For more than 40 years, we have redefined innovation with the world's most advanced memory and semiconductor technologies. We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.
Job DescriptionWe are seeking a highly experienced Analog Layout Engineer for our Advanced DRAM Development Team in Hyderabad, India. As a critical member of the core DRAM leadership team, you will play a pivotal role in our success. Your expertise will contribute to the successful realization of pioneering semiconductor products, enabling us to maintain our competitive edge in the industry.
Key Responsibilities:- Design and develop complex Application-Specific Integrated Circuits to meet our product specifications and requirements for High Bandwidth Memories, working for intensive applications such as artificial intelligence and high performance computing solutions.
- Familiarity with the principles of die design is essential to create effective and efficient layouts.
- Industry Involvement: You actively participate in standards committees, representing Micron and staying informed about industry developments.
- Leading Project Layout Team: You lead the establishment and growth of a layout team to meet Micron's global DRAM layout requirements.
- Technical Expertise: Your understanding of high-speed interface principles, mixed-signal design, and off-chip signaling is crucial.
- Attention to Detail: You approach IC layout design with passion, ensuring architecture analysis and optimization for performance, power, and area.
To be successful in this role, you should have:
- 15+ year experience in analog/custom layout in advanced CMOS process.
- Minimum 4+ years developing teams and project experience.
- Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
- Strong skills in layout and floor planning skills and manual routing.
- Excellent verbal and written communication skills required.
- Capable of working in a multi-functional, multi-site team environment in multiple time zones.
B.E or M.Tech in Electronic/VLSI Engineering.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
Estimated SalaryThe estimated annual salary for this position is ₹20,00,000 - ₹30,00,000 depending on qualifications and experience.
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