Optimizing Core Architectures

5 days ago

Vadodara, Gujarat, India beBeeMemoryLayout Full time ₹ 1,80,00,000 - ₹ 2,50,00,000
Job Description

We are seeking a skilled Memory Layout Engineer to join our team. As a key member of our design team, you will be responsible for developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding Power, Performance, and Area (PPA) metrics.

This is an exciting opportunity for a highly motivated individual who is passionate about memory layout engineering and wants to make a significant impact in the field.

Key Responsibilities:
  • Design and develop memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores.
  • Collaborate with cross-functional teams to propose changes based on layout implications.
  • Explore possible floor planning options and propose improvements.
Requirements:
  • Master's degree in Electronic Engineering or equivalent from a reputable University or Engineering School.
  • Minimum 5 years of experience in SRAM / memory layouts creation and backend verifications including EMIR analysis.
  • Strong understanding of CMOS Transistors, their behaviors, and CMOS logic design and layout.
  • Ability to create high-quality design rule-driven layouts.
  • Good interpersonal skills and ability to work effectively in a team environment.
Nice-to-Have Skills:
  • Basic knowledge of scripting languages, such as Perl or Python.
  • Experience working on Cadence or Synopsys flows.

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