Chip Design Optimization Lead
1 week ago
At Modernize Chip Solutions (MCS), we are seeking an experienced Senior Physical Design Engineer to lead our chip design optimization efforts. This is a senior-level position that requires a minimum of 15+ years of experience in SoC Physical Design.
We are looking for someone with hands-on experience in advanced FinFET node designs, specifically 7nm/5nm/3nm. The ideal candidate will have expertise in Cadence/Synopsys PnR/STA tools and Calibre, as well as strong scripting/automation skills.
This role involves working on floor planning, bump planning, pin assignments, feed through, LFU optimization, and resolving critical design and execution issues related to physical verification/implementation and sign-off. Our team works closely with the package team to optimize the bumps and ensure seamless integration.
The successful candidate will have a strong track record of performing floor-planning and routing studies at block and full-chip levels. Experience with pushing down top-level floorplans and clock trees to partitions is also essential. Additionally, the ability to work with power planning, IO/bump planning, pad ring creation, die file creation, and RDL routing is crucial.
We estimate the salary for this position to be around $250,000 per year, considering the location in Hyd/BLR and the level of experience required. We offer a competitive benefits package and opportunities for professional growth and development.
If you are a seasoned physical design engineer looking to take on a leadership role and drive innovation in chip design optimization, we encourage you to apply for this exciting opportunity.
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