High-Speed PLL Digital Design Engineer and Specialist
2 weeks ago
Job Overview
Qualcomm India Private Limited seeks a skilled High-Speed PLL Digital Design Lead Engineer to join its Engineering Group in Hardware Engineering.
Responsibilities
- Design and implement high-speed PLLs using RTL, ensuring compliance with linting, clock-domain crossing, low-power, and DFT rules.
- Work closely with the functional verification team to develop test plans and debug hardware designs.
- Create timing constraints, deliver synthesized netlists to physical design teams, and provide constraint support for PD STA.
- Develop UPF files, perform power-aware equivalence checks, and conduct low-power checks.
- Insert DFT and conduct ATPG analysis to achieve optimal SAF and TDF coverage.
- Provide support for SoC integration and chip-level pre/post-silicon debugging.
Requirements
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field, along with 4+ years of experience in hardware engineering, or equivalent qualifications.
- Mastery of micro-architecture development, RTL design, front-end flows (lint, CDC, low-power checks), synthesis/DFT/FV/STA, and post-silicon bring-up and debug.
- Excellent communication skills and ability to work effectively across global teams.
Estimated Salary Range
$120,000 - $180,000 per year, depending on experience.
Benefits
Qualcomm offers an equal opportunity workplace, accommodations for individuals with disabilities, and competitive compensation packages.
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