Senior Cache Architect
2 days ago
We are seeking a highly skilled CACHE SYSTEM LEAD to lead the architecture, design, and development of high-performance processor L2 and LLC (Last Level Cache) systems.
About Mulya TechnologiesMulya Technologies is a leading provider of innovative technology solutions. As a Fortune 100 company, we have a strong commitment to delivering cutting-edge products that meet the evolving needs of our customers.
Responsibilities- Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements.
- Develop the features, present the proposed architecture in the High level design discussions.
- Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature.
- Signoff the Pre-silicon Design that meets all the functional, area and timing goals.
- Participate in silicon bring-up and validation of the hardware.
- Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums.
- Estimate the overall effort to develop the feature.
- Estimate silicon area and wire usage for the feature.
- #ISAIS 8 to 20 years of relevant experience
- At least 1 generation of processor L2 cache or LLC design delivery leadership.
- Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP.
- Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations.
- Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory.
- Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.
$175,000 - $250,000 per year, depending on location and experience.
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