Senior Microarchitecture Designer for High-Performance Interconnects

1 week ago


Bengaluru, Karnataka, India Mulya Technologies Full time

Job Overview

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Mulya Technologies is seeking an experienced Logic design lead to develop a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect.

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This individual will be responsible for designing and architecting different interconnect topologies as driven by bandwidth, latency, and RAS requirements.

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Responsibilities:

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  • Develop the features and present the proposed architecture in the High-level design discussion
  • Design micro-architecture and RTL, collaborating with Verification, DFT, Physical design, FW, SW teams to develop the feature
  • Sign off Pre-silicon Design that meets all functional, area, and timing goals
  • Participate in silicon bring-up and validation of the hardware
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Requirements:

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  • 6-15+ years of relevant experience
  • At least 1 generation of processor interconnect design delivery leadership (e.g., UPI, axi, amba, NoC)
  • Expertise in SMP coherency and various snoop and data network protocols
  • Understanding of latency & bandwidth requirements and effective means of implementation
  • Working knowledge of queuing theory numa/nuca architecture and proficient in HDLs - VHDL / Verilog
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Salary Range: $150,000 - $200,000 per annum

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Location: Bangalore



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