Senior Microarchitecture Designer for High-Performance Interconnects
1 week ago
Job Overview
">Mulya Technologies is seeking an experienced Logic design lead to develop a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect.
">This individual will be responsible for designing and architecting different interconnect topologies as driven by bandwidth, latency, and RAS requirements.
">Responsibilities:
">- Develop the features and present the proposed architecture in the High-level design discussion
- Design micro-architecture and RTL, collaborating with Verification, DFT, Physical design, FW, SW teams to develop the feature
- Sign off Pre-silicon Design that meets all functional, area, and timing goals
- Participate in silicon bring-up and validation of the hardware
Requirements:
">- 6-15+ years of relevant experience
- At least 1 generation of processor interconnect design delivery leadership (e.g., UPI, axi, amba, NoC)
- Expertise in SMP coherency and various snoop and data network protocols
- Understanding of latency & bandwidth requirements and effective means of implementation
- Working knowledge of queuing theory numa/nuca architecture and proficient in HDLs - VHDL / Verilog
Salary Range: $150,000 - $200,000 per annum
">Location: Bangalore
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