
Chief Memory Architect
5 days ago
Job Opportunity:
We are seeking an experienced Memory Design Engineer to join our team.
As a key member of the organization, you will be responsible for creating innovative memory architectures and designs.
The ideal candidate will have hands-on experience with full custom memory design, characterization, layout design, net-lister, and SRAM design verification at the compiler level.
Key responsibilities include ensuring the execution plan, design quality plan, and DFMEA are up-to-date, and publishing project health along with reporting any risks and mitigation strategies.
Required skills include knowledge of different memory architectures, expertise in working on SRAM leafcell GDS from scratch to top-level integration, and proficiency in physical verification flow debug.
A strong understanding of Cadence Virtuoso layout editor and Caliber Physical Verification Flow is essential, as well as experience with Synopsys Custom Compiler and good knowledge of layout practices in lower process nodes.
Additionally, you will work on FinFET architecture, address process-dependent effects, optimize layouts for yield enhancement and manufacturing robustness, and create detailed physical layouts for memory cells, arrays, and peripheral circuits.
This is an excellent opportunity to utilize your skills and expertise in memory design.
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